Senior Digital Physical Design Engineer
This is a fascinating opportunity for a Senior Digital Physical Design Engineer to join a multinational company developing complex chip designs for the space industry - arguably the most exciting industry in the world.
Based in Manchester, this position would suit an experienced Digital Physical Design Engineer capable of undertaking a technical lead role for a small team, and owning the physical implementation of complex ASIC designs and testchips across multiple process technologies. This team uses Cadence tools, however Synopsys or Cadence users will both be considered. This company is set to grow throughout 2019 - it's a great opportunity to join a fast growing team that can offer real career prospects for growth within a global company.
The Senior Digital Physical Design Engineer will be well-versed in the RTL-GDSII flow, with expertise in the following:
· Synthesis, Floorplanning, Place and Route (P&R), Clock Tree Synthesis (CTS), Parasitic Extraction, Static Timing Analysis (STA) & Timing Closure, Physical Verification, Power Analysis, Formal Verification and ATPG insertion/pattern generation
· Chip level partitioning and assembly
· Cadence / Synopsys design environment
· Scripting languages (Tcl/Python/Perl etc.)
· Liaising with other design teams, third party IP suppliers and EDA tool vendors
Relocation assistance within the EU can be provided.
Contact firstname.lastname@example.org for details, or call +44 (0)1189881152.