IC Resources Ltd

Analog & AMS Verification CAD Engineer - Contract

Location
Austria
Salary
€55 - €65 per hour + 12 month contract
Posted
10 Aug 2017
Closes
07 Sep 2017
Ref
J42764
Contact
Rob Maw
Job Function
Design
Specialist Area
Analogue, CAD, Semiconductors
Contract Type
Contract
Hours
Full Time
Analog & AMS Verification CAD Engineer
Contract/Freelance Role
Austria
€55-65 per hour

IC Resources is currently working with a global semiconductor company looking for a freelance / contract Analog & AMS Verification CAD Engineer.

The role will involve you working with an international team and give you the opportunity to work on multiple technical aspects including deployment, tactical support and new solution introduction. You will also be asked to pro-actively put in place and support and new solutions integration.

You will have experience in; Analog & Mixed Signal Front End CAD designer, Cadence Virtuoso schematic, ADE-L / XL , Hierarchy Editor , Simulator (Spectre - Incisive (AMS), AMS Functional Verification and test regression (Incisiv, vManager, vPlanner, VCS-AMS), AMS Model Development, Wreal, SystemVerilog, VerilogAMS and UVM.

You will have experimented with Cadence and Synopsys verification tools for digital and AMS functional test regression and if you have used Notion Python, Cadence Skill or Shell languages this would be beneficial

The contract is initially a 12 month contract and the client would be very interested in candidates who can commit to on-site work, however there is the option to work 1-2 days remotely. You must be an EU national to be considered for this position.

Key Points
- Analog & AMS Verification
- CAD Engineer
- Deployment, tactical support and new solution introduction
- Put in place and support new solutions
- Analog & Mixed Signal Front End CAD design
- Cadence Virtuoso Schematic
- AMS Functional Verification and test regression
- System Verilog, VerilogAMD, UVM
- 12 month contract
- On-site work in Austria, can have 1-2 days remote working
- EU Candidates only

If you would like any further information on this role please contact Rob at IC Resources

Notes - Analog, AMS, Verification, CAD Engineer, CAD Design, Cadence Virtuoso, Schematic, Analog & Mixed Signal, Front End Design, CAD Design, Function Verification, System Verilog, VerilogAMD, UVM, 12 Month contract, Austria

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