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RTL Engineer, Cambridge
We are searching for an experienced RTL Engineer to join a strong team and to work with cutting edge technologies.
We are searching for an RTL Engineer with the following profile:
Good and relevant academic background
More than 2 years of relevant DFT experience
Experience on multiple VLSI implementation projects
Good understanding of DFT for digital designs and the tradeoffs involved.
Experienced in using Verilog HDL and some experience of Logic Synthesis, Constraint development and STA.
Proficient in Scan based test, compression and ATPG using Mentor or Synopsys DFT tools.
Experience in Memory BIST and JTAG.
Interest or experience in the following:
Logic BIST, Interface test, Boundary scan, Memory repair, Analog test, interface testing.
Experience in test pattern generation and understanding of ATE capabilities.
Diagnosis and debug of silicon issues.
DFT flow development experience.
Perl and TCL use.