Digital Verification Engineer
Fantastic career opportunities for Verification Engineer's within the CPU and SOC development teams of a leading wireless communication business in Ireland. As a Verification Engineer you will have experience in developing unit and SoC level test benches using System Verilog / UVM. Joining as a Verfication Engineer there is great career growth within this organisation as they are rapidly growing the team in Ireland as well as having multiple R&D sites around the world. As a Verification Engineer you will have the opportunity to mentor junior engineers should this be something that interests you.
The ideal candidates will have :
· Experience in developing unit and SoC level test benches using OVM/UVM
· Constrained random functional verification environment in System Verilog
· Experience in Gate Level Simulation (GLS) verification flow for SoC verification.
· Experience of pre and post-silicon verification testflow and automated test benches
· Strong knowledge of test-plan generation, coverage analysis transaction level modelling, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog
· Verilog, C/C++, System C, Java, TCL/Perl/shell-scripting required
· Building and leading verification teams is a plus
· RTL design and front end design flow experience
· Excellent communication skills
Please note that you must be committed to working on-site in Ireland for this role. There is an opportunity for visa sponsorship for this position.
For further information please contact Rob at IC Resources.