As a Power Engineer within the CPU Development team, this is a superb opportunity to join a global, fabless semiconductor, leader developing SOC's in the most advanced technology nodes for future generation connected-devices.
You will apply your experience in low power design and Power Analysis to create vectors in C/C++ and Assembly, run tests and analyse results, with a view to design optimisation of power consumption for all development phases from design to tapeout.
Key skills and qualifications I am looking for include:
- Extensive experience in DV (RTL, 0delay, SDF), Power analysis and reduction techniques using Primetime PX, PowerArtist is required
- Experience with low power implementation techniques
- Dynamic clock and voltage scaling Power analysis (Leakage and dynamic) and Thermal analysis
- Proficiency in Verilog/System Verilog coding, verification techniques, and scripting language, such as: Perl, Python, Tcl, and Make etc
- Arm Assembly
- Post-Silicon power measurement
- Experience with CPU micro-architecture, Benchmarks and their power challenges
- Experience in Thermal analysis
For any queries, questions or to have a confidential discussion please contact David Dixon - Digital SOC Recruitment Consultant
Tel: +44 (0) 118 988 1153