As an STA Engineer, this is a superb opportunity to join a global, fables semiconductor, leader developing SOC's in the most advanced technology nodes for future generation connected-devices.
You will use your experience in STA (Static Timing Analysis), to help shape the way STA is conducted for advanced technology, 7nm, processor based SOC's, using your understanding of semiconductor devices, tools and flows, to drive the timing closure and signoff of complex mixed-signal SOC's.
Key skills and qualifications I am looking for include:
- Timing analysis, Timing Sign off and Timing Convergence execution experience
- Experience with all aspects of STA of SoC or Processor designs.
- Good understanding of library, derates, AOCV/POCV and intricate dependency on timing analysis
- Clear and deep understanding of the constraints and impact on timing.
- Experience in working with advanced process nodes (14 nm and below)
- Familiar with circuit SPICE modeling
- Familiarity with timing and power ECO techniques
- Ability to understand any STA tool (Synopsys/Cadence/Mentor etc.)
For any queries, questions or to have a confidential discussion please contact David Dixon - Digital SOC Recruitment Consultant
Tel: +44 (0) 118 988 1153
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