Design Flow Development Engineer
A Superb opportunity for a Design Flow Development Engineer to join the world's most revered fabless Semiconductor companies developing best-in-class SoC solutions for The Internet of Things.
My clients Design Flow Development team defines and enables the RTL to GDSII implementation flows for variety of advanced low power and high performance SOCs, enabling state-of-the-art mobile chipsets.
The Design Flow Development team is looking for outstanding engineers with experience in Physical Design for High performance and/or lower power cores and aptitude for debug design issues and enable seamless quality of tools and flows. The candidate will drive best-in-class RTL to GDSII flows qualification for >1billion device SOCs in 10nm and smaller FinFET technologies. If you have expertise in these areas and are excited by driving leading edge semiconductor technologies to real life, this is the opportunity for you.
Key skills and qualifications I am looking for include:
- Hands-on expertise in P&R for block and top level integration.
- Strong CAD automation using: Python, Tcl/Tk, PERL, HTML, C++
- Power grid, clock tree, and low-power reduction implementation methods
- Signal integrity and timing closure issues such as OCV/AOCV/Statistical Timing and Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.)
- Floor planning, Placement, CTS, P&R
- Must be an expert in Synopsys or Cadence
For any queries, questions or to have a confidential discussion please contact Rachel Mason - Digital ASIC Design Recruitment Consultant
Tel: +44 (0) 118 988 1107
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