Design Verification Engineer
Design Verification Engineer with experience using advanced IC verification techniques sought to join a small UK IC Design team of a large semiconductor parent.
You will have the opportunity to own all aspects of verification through test plan specification, test/testbench implementation and debug.
To be successful within this Design Verification role, you're experience will cover some of the following :-
Advanced verification techniques (constrained random testing, assertion based verification)
Code and functional coverage, C/C++, UVM, Formal verification
RTL design (verilog preferred), RTL and gate level simulation and debug
UNIX scripting (C-shell, PERL), Emulation
Candidates must have the right to work in the Eu. Please contact Dave Dixon at IC Resources for more information.