IC Resources Ltd

Digital ASIC Design Engineer

Competitive salary
19 Jul 2018
16 Aug 2018
Caroline Pye
Job Function
Specialist Area
FPGA & ASICS, Hardware
Contract Type
Full Time

Digital ASIC Design Engineer - Switzerland

Excellent salary, plus benefits

Our superb IC Design client is recruiting for a Digital IC Design Engineer to join them in the French-speaking region of Switzerland.

This company has a long, very successful track-record manufacturing ASICs and system solutions for a huge range of applications areas, from sensor ICs, displays, ultra-low power microcontrollers to communication and automotive applications. Based in an attractive region of Switzerland, close to lakes, wooded mountains and a vibrant town, they offer excellent opportunities for Digital IC Design Engineers to work on all stages of the design flow process in challenging technologies.

The main function of your role will be frontend RTL design and verification using UVM methodology. You will support the Design Lead in the product definition and design execution, interface with remote design teams and interface with the quality, design services, fab, and back-end design groups. You will have the chance to broaden and hone your design skill set, and enjoy working within a friendly, pragmatic company culture which encourages ideas and accountability.

Requirements include:

· A University degree (BSc / MSc / PhD) in Electronic Engineering, or related field

· Strong skills in RTL design (VHDL / Verilog) with a solid knowledge of digital IC design and verification methodology

· Strong autonomy, and excellent team work skills

· A versatile, adaptable working style, with a keen interest and ability to work on different stages of the design flow

· Good interpersonal skills, and an ability to communicate well with external groups

· Excellent language skills in English

Given the breadth of design opportunities on offer within this company, you'll be continually challenged and engaged. For details, please contact Caroline @ IC Resources

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