IC Resources Ltd

Senior Analog IC Layout Engineer

Depending on experience
23 Jan 2018
19 Feb 2018
Ane Bauer
Job Function
Specialist Area
Contract Type
Full Time

Senior Analog IC Layout Engineer

Munich, Germany

Salary depending on experience

A new opportunity for a Senior Analog IC Layout Engineer to join a world leading company looking to expand their design team in Munich. The Senior/Principal Analog Layout Engineer will work on layout and verification of Analog IPs for complex System-on-Chip products as well as supporting top level layout of complete Mixed Signal System-on-Chip products.

You will:

- be responsible for the layout of Analog IC blocks, block level and top-level layout, verification parasitic extraction, DRC, LVS, and DFM procedures.

- work on block level and top-level floorplanning alongside other designers and will be involved with reviewing the IC Layout for power routing, electro-migration, signal path check and coupling.

In addition you will run top-level layout integration and verification.

- be industry degree qualified and have a minimum of 5+ years experience in Custom Analog IC Layout with solid knowledge on CMOS technologies below 40nm.

- be knowledgeable in techniques for device matching, parasitic extraction and high power routing.

You should have a strong level of proficiency in interpreting Calibre, DRC, ERC, LVS.

- have a good understanding of RC delay, electro-migration, and cross-capacitance as well as guard-rings, DNW, PN junctions and advanced process effects such as LOD, WPE.

Skills in scripting languages like Perl, Skill or Ample are a beneficial to your successful application.

You should be a capable leader of other layout engineers in the area of top-level integration.

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