IC Resources Ltd

Senior Digital Physical Design Engineer - Ireland

Location
Republic of Ireland
Salary
Excellent salary + Bens
Posted
31 Aug 2018
Closes
28 Sep 2018
Ref
JO-1807-133239
Contact
Caroline Pye
Specialist Area
FPGA & ASICS
Contract Type
Permanent
Hours
Full Time

Excellent salary, plus generous benefits and relocation

Senior Digital Physical Design Engineer - Southern Ireland


A superb opportunity for a Senior Digital Physical Design Engineer to join the world's most revered fabless Semiconductor companies developing best-in-class SoC solutions for the Internet of Things.


This is without a doubt a hugely challenging, exciting and visible role, in which you will take ownership of advanced implementation technologies and flows for Synthesis and Place and Route, enabling flawless quality of tools and flows.


The role is within a brand new team within this expanding silicon design centre, located in an attractive, vibrant city on the Southern Irish coast. We're looking for an outstanding Physical Design expert to join as one of the key people within this new group. Our client looks to hire industry's best, and is looking for someone to develop best-in-class RTL to GDSII flows for over 1billion device SoCs down to 7nm technologies.


Essential for this position:


· A successful track record working in industry as a Physical Design Engineer for digital ASICs

· In-depth knowledge of the entire physical design flow from RTL to GDS (including Floorplanning, Power planning, Place and Route (P&R) Clock Tree Synthesis (CTS), Post route optimization and DRC closure

· Strong ability solving complex design issues

· RTL coding skills

· Strong CAD automation skills using: Python / Tcl/Tk or PERL


As the successful candidate you'll receive an excellent salary and benefits package, generous relocation assistance and enjoy working within a very friendly, dynamic team with a great employee culture. Work permit sponsorship can be provided for candidates already based in the EU.


For details, please contact Caroline Pye @ IC Resources for a confidential discussion.


Key words: Digital, Physical Design, ASIC, Backend, Physical Implementation, RTL, GDS2, GDSII, RTL-GDSII, floorplanning, Place & Route, routing, P&R, PnR, synthesis, clock tree, tapeout, timing closure, STA, static timing analysis, SoC, DFT, design for test, EDA, Synopsys, RTL, coding, perl, tk, tcl, Python, clock tree synthesis, CTS, physical verification, netlist, CAD, CMOS, Semiconductor, Ireland, Cork, Europe.

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