IC Resources Ltd

Senior Digital Design Engineer

Location
Cambridge
Salary
Competitive salary
Posted
27 Jul 2018
Closes
24 Aug 2018
Ref
JO-1806-133067
Contact
Andrew Emberson
Specialist Area
FPGA & ASICS, Hardware
Contract Type
Permanent
Hours
Full Time

Team Lead Design Engineer

Competitive salary range

Cambridge


Are you bored of the repetitive tasks in your current day to day job or just curious about what job opportunities are floating around on today's current market? If so I might just have the exciting and unique job opportunity for you.


Our client is working on very exciting technology based in the Image Processing industry that will revolutionize the technology industry as we know it. This company are looking to expand their Digital Design Team and they have requested an engineer who has worked on ASIC or FPGA Design to lead this team. Located in Cambridge, this company needs a highly analytical thinker who has had over 6 years relevant experience working or ASIC's or FPGA's. There is no need for prior team lead experience but you will need to posses the desire to want to lead a team and have strong communication skills


Our client is developing the latest innovative image and video products and their digital design team is rapidly expanding so do not miss your chance to apply. You will work alongside highly skilled engineers and gain valuable experience working on cutting edge technology from an established semi conductor company.


The successful candidate will have:

* Over 6 years of experience using Verilog or VHDL coding for FPGA or ASIC's.

* A good academic record (1st / 2:1 grade required) in Electronics or related field.

* You're likely to come from a similar project led production environment in Technology,

* Desired skills would be some software experience in either C++ or Python.


If you're even a tiny bit curious, and you have experience in FPGA or ASIC and predominantly code in VHDL then please apply now.


For further details about this opportunity please contact me at IC Resources.