IC Resources Ltd

Senior Digital ASIC Design Engineer

Location
London
Salary
Competitive salary + benefits
Posted
26 Jul 2018
Closes
15 Aug 2018
Ref
JO-1806-133024
Contact
Caroline Pye
Job Function
Design
Specialist Area
FPGA & ASICS
Contract Type
Permanent
Hours
Full Time

Senior Digital ASIC Design Engineer

Competitive salary + benefits

Central London


Our client, an exciting mixed-signal ASIC start-up based in Central London near Regents Park, is looking for a Digital ASIC Design Engineer to join them.


As a small, fast-paced technology company, our client is looking for a highly talented, capable RTL Design Engineer to play a big role in developing complex digital blocks on their mixed-signal IC. You'll take charge of all areas of development for custom digital blocks for ultra-low power applications, with particular focus on design specification, RTL design (VHDL) and testing. This role has quite a strong research focus, and will offer the right candidate the opportunity to write white papers and have their research published in academic journals.


Required:


· Top notch RTL coding skills for ASIC designs (VHDL / Verilog)

· Excellent academics; a good degree (1st / 2:1) in Electronics or related field

· Several years' hands-on design experience within industry

· A track-record of delivering successful chip development cycles

· Experience of backend design processes would be beneficial, but not essential.


If you're looking for an opportunity to gain valuable digital design experience in a start up environment and work in the City, get in touch for more details.

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