Low Power Methodology Engineer
Digital ASIC Design Engineer - Low Power Methodology
Excellent salary + benefits
This is a superb opportunity for a Digital ASIC Design Engineer with experience working on low power chip design to join a global technology giant based in Ireland.
This is a chance to join THE world's top wireless high tech company and develop wireless ICs for next generation devices.
Our client is undergoing monumental growth of their Irish design centre this year, and currently seek several Digital ASIC Design Engineers with low power / power management expertise to join them. In this role you will be designing low power IP blocks including AVS (adaptive voltage scaling), ACD (adaptive clock distribution), on-chip sensor controller, digital power meter, and embedded voltage regulator controller.
Key requirements for this position include:
- A degree (BSc / MSc / PhD) in Electronic Engineering / Computer Science or related field
- Prior industrial experience working on low power digital ASIC design
- Frontend RTL design expertise (VHDL / Verilog / SystemVerilog)
- Good knowledge of low power design standards such as UPF / CPF
- A detailed knowledge of circuit analysis and logic design
- Clear communication skills in English
As a location, this city was recently named as one of Europe's culturally vibrant. There is a thriving electronics community, a huge range of sporting, culture and leisure amenities and stunning countryside and coastal landscapes nearby. It's great for families, as well as single individuals, with a lot going on.
You'll receive a very competitive salary package and a whole host of benefits.
For details, contact Caroline @ IC Resources for more information.