Junior Verification Engineer
Digital IC Design Engineer
€Competitive salary upon experience, plus benefits
This is an opportunity for an experienced Digital IC Verification Engineer to join a rapidly expanding company based in the picturesque and highly desired French-speaking part of Switzerland.
* An understanding of System Verilog and UVM methodology
* Experience in RTL coding in Verilog or VHDL
* Experience in functional and code coverage.
You will be self motivated with a strong sense of ownership and responsibility. Good communication skills in English is ideal with knowledge of the French language an advantage.
If you have passion for technology, thrive off new challenges, and seek the next step in your career; please contact email@example.com to apply now!