FPGA Verification Engineer(SystemVerilog/UVM)-Paris
7 days left
- Full Time
FPGA Verification Engineer (SystemVerilog/UVM)
My client is a well established organisation developing communication systems for 5G networks. Within their offices in Paris, they are seeking an experienced Verification Engineer to join their team Ideally, you will have experience as a Verification Engineer, with an excellent understanding of SystemVerilog and UVM. Previous exposure working with FPGA's, within a 4G/5G/LTE technology domain would be an advantage.
My client is willing to support relocation of candidates who have no working restrictions and are currently in the EU.
Please contact Dave at IC Resources for more details.
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