IC Resources Ltd

ASIC Senior DFT Engineer - Reading

Location
Reading
Salary
Competitive salary + benefits
Posted
16 Nov 2017
Closes
13 Dec 2017
Ref
JO-1710-118474
Contact
Caroline Pye
Specialist Area
FPGA & ASICS, Semiconductors
Contract Type
Permanent
Hours
Full Time

ASIC Senior DFT Engineer - Design for Test

Reading

Competitive salary, benefits


This a rare and exciting opportunity for a Senior DFT Engineer to join a brand new chip design centre based in Reading.


For our client's emerging UK branch, we are looking for a Senior DFT Engineer to join an expanding backend group providing full RTL to GDSII flow. As the first DFT expert to join this new team, you will work with the chip architecture team to define DFT specifications and the chip test interface. You will own the complete DFT solutions within chip design projects, and subsequently grow the DFT team around you as the centre expands.


Required:

* Extensive industrial Design for Test experience - essential

* Knowledge of industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time

* Solid knowledge of industry standards DFT and design tools

* Experience in debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG/1500 related issues

* Knowledge of Verilog and/or VHDL, and experience with simulators and waveform debugging tools


For more details, contact Caroline @ IC Resources


Our client can only consider candidates eligible to work in the UK for the time being.