IC Resources Ltd

Principal Analog IC Layout Engineer/Layout Lead - USA

Location
California
Salary
Salary depending on experience
Posted
18 Sep 2017
Closes
13 Oct 2017
Ref
J43393
Contact
Ane Bauer
Specialist Area
Analogue, Semiconductors
Contract Type
Permanent
Hours
Full Time
Principal Analog IC Layout Engineer/Layout Lead
California, USA
Salary depending on experience

This is a great opportunity for a Principal level Analog IC Layout Engineer to join a successful company involved in high performance Analog/Mixed Signal ICs for the consumer electronics market in the United States to lead layout projects from floor planning through to foundry submission.

In this role you will be leading a team of Layout Engineers and be involved with all Layout activities including top, cell and block level creation, edit and full verification (DRC, ERC, ANT, LVS and PEX) using state-of-the-art layout techniques for matching, ESD, latch-up prevention and parasitic reduction state of the art layout techniques for matching, parasitic reduction, yield optimization and ESD robustness in any project you are responsible for.

You will further support the project manager with provisional estimates for task durations, assign engineers to tasks, provide feedback on block and chip level progress and resolving bottlenecks in plan. Highlight any risks you see as soon as they arise and work alongside Project Manager and TPL.

The successful candidate will have around 8 years of experience in block level through to top-level layout, including floor planning, power routing and full verification prior to tape-out as well as the following:
-Thorough understanding of the impact of the layouts in terms of yield and financial implication.
-Proven experience of successful management of all layout tasks throughout a project, ensuring that the required quality is delivered to schedule.
-Expert process knowledge, use of CAD tools and layout techniques through quality and pace of work.
-Competence and expertise in providing layouts to deadline as defined by project plans.

For further information and to apply please contact ane.bauer@ic-resources.com with your full CV.

Applicant with experience in: Analog, analogue IC Layout, CAD, DRC, ERC, ANT, LVS, PEX, ESD, project leading, will be considered for this opportunity. Location: Francisco Bay area