IC Resources Ltd

Design Verification Engineer

M√ľnchen (81249)
Salary dependent on experience
03 Aug 2017
31 Aug 2017
Seamus Hayes
Job Function
Specialist Area
Contract Type
Full Time
Salary dependent on experience##

Design Verification Engineer - Munich

This is a new and exciting opportunity for a Digital Verification Engineer to join a global leader in Semiconductor development based in Munich. As a member of design verification team, you will have the responsibility for construction of verification environments, coding of test scenarios and assertions. In this capacity, your role will involve close collaboration with analog and digital design engineers. Excellent communication skills in English are required with knowledge of the German language an asset.

Key Qualifications:

- Typically requires a minimum of 5 years of experience in System Verilog or the other verification language
- Hands-on experience with constrained random verification environments.
- Hands-on experience with Assertion Based Verification
- Basic design background in support of verification results analysis.
- Knowledge of Object Oriented Programming
- Knowledge of any one of verification language (UVM, OVM, or VMM) is a plus.
- Familiarity with system design using C(C++) or Verilog is a plus.
- Hands-on experience with formal verification (assertion-driven verification) is a plus.
- ATE functional test pattern generation for logic testers is a plus.


Construction of verification environment by using Verilog, System Verilog or UVM Designing test plan for verification Coding test scenarios, assertion and debugging for Digital Design.


BSc or MSc in Electrical Engineering is required or equivalent experience

For more information or to apply please contact Seamus Hayes at IC Resources.

Keywords; Munich, Semiconductor, Design Verification, Test, System Verilog, Object Oriented Programming, UVM, OVM, VMM, C/C++

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