IC Resources Ltd

Senior Digital Physical Design Engineer

4 days left

Location
Bristol
Salary
Excellent salary
Posted
25 Jul 2017
Closes
22 Aug 2017
Ref
J40223
Contact
Caroline Pye
Job Function
Design
Specialist Area
FPGA & ASICS
Contract Type
Permanent
Hours
Full Time
Senior Digital Physical Design Engineer - new IC team
Bristol
Excellent salary

We are looking for top-class Digital Physical Design Engineer to join a brand new silicon development team. This is an outstanding opportunity if you are looking for a fresh challenge within a new technology space.

Based in Bristol, UK, this is a new silicon design team focusing on the delivery of bespoke networking solutions. Our client is an established financial company with a strong history in technology development, branching into new fabless silicon design activities. Challenges abound, our client is working on some truly revolutionary technology, and needs top class ambitious engineers who will thrive in a role which combines responsibility for decision making and execution.

Required:
*A good degree from a leading university in an engineering or computer science related discipline.
*A number of years' Digital Physical Design experience, with sound knowledge of RTL through to final GDSII flow
*Expert skills in static timing analysis (STA), floorplanning and Place & Route (P&R)
*Excellent understanding of CMOS silicon digital chip design and implementation
*An understanding of custom / transistor level design would be advantageous

You will be working with some of the most brilliant and talented people industry has to offer. This role offers a lot of technical freedom and scope for innovation.

Along with an excellent salary, this opportunity will value and reward you for your contributions and support your career progression.

Please contact Caroline Pye for more detailed information.

Bristol-based opportunity for a Digital Physical Design Engineer with the following: Digital, Physical Design, Backend Design, Implementation, ASIC, RTL, GDSII, GDS2, STA, timing, static timing analysis, timing closure, tape-out, floorplanning, Place & Route, P&R, PnR, CMOS, layout,, silicon, custom, semi-custom, transistor, cell libraries, memory, tcl, perl, scripting, EDA, Bristol, South West, UK.

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