IC Resources Ltd

ASIC Design Engineer

Location
Austria
Salary
€50 - €60 per hour + 6 Month Contract
Posted
11 Jul 2017
Closes
27 Jul 2017
Ref
J41773
Contact
Harshiv Harji
Specialist Area
FPGA & ASICS
Contract Type
Contract
Hours
Full Time
Digital IC Design Engineer
Austria
6 month contract
€50-60 per hour

IC Resources is currently working with a client based in Austria, looking for experienced Digital IC Design engineers for an initial 6 month contract starting ASAP.

Our client is looking for candidates with experience in working with RTL design using Verilog and VHDL. As one of the engineers you will need experience in RTL design and development, and you would be responsible for implementing design blocks in RTL to the required level. You will also be required to create verification environments within this project, to test functionality so experience with SystemVerilog and being able to write the synthesis scripts is essential. If you have experience with UVM this is extremely beneficial.


Key Points
- Experience in RTL design using Verilog / VHDL
- Experience with Synthesis Scripts, SystemVerilog
- DFT, UVM and STA would be beneficial
- 6 month contract

You must be eligible to work in Austria for this role, if you would like more information or to apply for this role please contact Harshiv Harji at IC Resources.

***Please note that if you are interested in the following: Digital IC Design, RTL Design, Verilog, VHDL, SystemVerilog, Synthesis, UVM, DFT, STA, Semiconductors, Austria, 6 Months Contract and you could commit to on-site work in Austria then this could be a good opportunity for you.***