Electronics Design Engineers (3 positions)
Electronics Design Engineers (3 positions)
STFC Daresbury Laboratory, Warrington, Cheshire
Salary £37,213–£44,072 (Senior Engineer), or £47,725-£53,028 (Principal Engineer) (dependent upon qualifications and experience and inclusive of annual allowance)
2 Years Fixed Term
The Science and Technology Facilities Council (STFC) is one of Europe’s largest research organisations. We are trusted to support, enable and undertake pioneering projects in an amazing diversity of fields. Through world-class facilities and people, we’re driving ground-breaking advances in science, technology and engineering.
Within STFC the Technology Department provides advanced technology and engineering in support of both STFC funded activities and other high profile international projects. Our technologies and competencies are world class, and our expertise encompasses micro-nano engineering, through microelectronics, to major engineering structures.
About The Role
Due to an increase in workload caused by exciting new opportunities at the European Spallation Source (ESS) the Detector Systems Group (DSG) within the Technology Department at our Daresbury laboratory requires 2 additional Electronics/FPGA Engineers with strong System, Board and FPGA level design skills (including high speed networking).
A further opportunity has arisen within DSG for an Electronics Engineer with strong Detector, electronics and FPGA design skills to work on DSG’s world-leading x-ray detector systems for synchrotrons.
DSG is a team of detector specialists with expertise in electronics and semiconductor radiation detectors. The group has facilities for high precision assembly of complex electronics and clean areas for detector assembly. Currently we are involved in a number of International Science projects such as the European Synchrotron Radiation Facility (ESRF), CERN as well as the ESS.
Working within DSG, you will be part of a team of engineers working with Synchrotrons in the UK, Europe and beyond, or with ESS and its partners across Europe, to implement a generic readout framework for novel Neutron detector technologies, often incorporating ASICs for digitisation.
For ESS electronics/FPGA roles, applications are typically based around the latest high end FPGA devices for signal processing and 10/100G Ethernet for data transport. Systems can range from a single FPGA to extreme DAQ systems with many thousands of FPGAs and 10/100G links feeding large CPU/GPU processing farms.
The electronics role within DSG requires a good working knowledge of semiconductor detectors and front end readout systems as well as competence in high speed FPGA design and programming.
As a senior engineer your responsibilities may range from leading or assisting in the architecting of a system, leading a small project team to implement a system or to undertaking tasks on an individual level such as designing a complex board or IP library block or undertaking a challenging FPGA implementation.
For the ESS roles, exceptional candidates, with extensive relevant experience, will be considered for appointment as Principal Engineers. You will be expected to take the lead role in any aspect of management, technical management, design or project life cycle. This would include bidding for work, dealing with the start-up of projects, Section line management, leading a project design team and leading technical areas such as design tools or design strategy.
All these roles may require UK and international travel. Some projects will also require the ability to work in a controlled radiation area.
Depending upon the size and nature of the system being built you may have individual responsibility for any mix of the Project Management, System Level Design, Board Level Design and FPGA design required by the particular project.
Successful applicants will be appointed at Senior Engineer or Principal Engineer level, depending on the strength of your skills, experience and qualifications.
Suitable candidates will hold a Degree in Electronics, Physics, Computer Science or demonstrate equivalent experience recognised by the award of Chartered Engineer status.
For the ESS roles you should ideally demonstrate experience and/or knowledge across high speed Networking, FPGA, DSP, HPC or Image/signal/data processing.
All candidates for the DSG role should ideally demonstrate experience and/or knowledge of several of the following areas in addition to FPGA skills: semiconductor radiation detectors, low noise analogue electronics, high speed digital electronics, embedded C programming, PCB design, 1Gb and 10Gb Ethernet based firmware design, Linux, Vacuum and cryogenics.
For all roles you will have strong FPGA design skills using the latest devices and vendor tool flows, along with proficiency in leading and/or implementing large complex Xilinx and/or Altera designs.
Expertise gained in an academic and/or industrial environment applied to Big Science DAQ/Processing Applications or other large Instrumentation Systems or large deployments would be beneficial.
Candidates should demonstrate Technical, Managerial, Personal Development and Leadership skills appropriate to the responsibility level applied for.
For consideration at Principal level you will demonstrate knowledge of Electronic/Optical/tool technology roadmaps/trends, along with System Design Skills optimizing hardware, firmware & software designs along with commensurate managerial and leadership skills.
Excellent communication, interpersonal and presentation skills are required to work with a range of colleagues and stakeholders.
An exceptional index linked pension scheme, 30 days leave allowance and flexible working are offered.
Applicants are required to include a cover letter outlining their suitability for this role. Please also state where you saw this role advertised.
Applications are handled by UK SBS; to apply please visit our job board at http://www.topcareer.jobs/Vacancy/irc241428_7244.aspx. Applicants who are unable to apply online should contact us by telephone on 01793 867000.
The closing date for applications is 23rd July 2017.