IC Resources Ltd

Senior / Principal Digital ASIC Design Engineer

Location
South West England
Salary
Competitive + bonus and benefits
Posted
19 Jun 2017
Closes
17 Jul 2017
Ref
J41935
Contact
Caroline Pye
Specialist Area
FPGA & ASICS
Contract Type
Permanent
Hours
Full Time
Senior / Principal Digital ASIC Design Engineer opportunity with leading UK Semiconductor firm
South West/M4 corridor location
Competitive + bonus and benefits

An excellent opportunity for an experienced Digital ASIC Design Engineer with a rapidly growing SoC design company developing high-class products for the consumer market.

In this position you will work on the full digital design flow of high quality audio and power management circuits in CMOS. Tasks include: digital RTL design, through verification, synthesis, DFT (design for test) , STA (static timing analysis) and Place & Route. Our client is looking for a proactive, senior level engineer; someone who takes responsibility for solutions and makes them happen.

The successful candidate will have a proven background in the design of digital ASICs, with expertise in VHDL and / or Verilog and complete experience in the full front-to-back end design flow. Experience in low power chip design would be a bonus, as would an understanding of analog or mixed-signal IC design. The role will include some travel from time to time to other European design sites.

An excellent salary is on offer with comprehensive benefits package (including pension, private healthcare and annual bonus).

For the right candidate, relocation assistance and visa sponsorship can be provided.

Email your CV for immediate consideration.

Key words: Digital, ASIC, IC, SoC, Design, RTL, VHDL, Verilog, Verification, Synthesis, timing closure, netlist, low power, Semiconductor, South West, UK.