Design for Test Implementation Engineer

Location
Toulouse
Salary
€40 - €50 per hour
Posted
11 May 2017
Closes
08 Jun 2017
Ref
DFT
Contact
James Witting
Specialist Area
Semiconductors
Contract Type
Contract
Hours
Full Time

Design for Test Implementation Engineer

Toulouse, France

6 month contract

€40-50/hour

The Company

A leading semiconductor company

The Role

  • Design For Test implementation with JTAG in an integrated circuit
  • Verification of the integrated circuit with the UVM methodology
  • Application of Power Management
  • Testability of integrated circuits
  • Description of the modules to be realized in Verilog and / or SystemVerilog
  • Content of state machine modules, sequencers, communication interfaces
  • Checking these modules in unit tests
  • Construction of the logic block global verification plan
  • Participation in the implementation of the audit plan
  • Verification methodology with UVM

The Individual

  • RTL for DFT
  • SystemVerilog
  • EManager / ePlanner of Cadence
  • UVM
  • JTAG
  • Experienced profile, autonomy, mixed signal DFT, UVM

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