IC Resources Ltd

Senior Static Timing Analysis Engineer - STA, Ireland

Competitive salary, plus bonus + benefits
16 Apr 2017
08 May 2017
Caroline Pye
Specialist Area
FPGA & ASICS, Semiconductors
Contract Type
Full Time
Senior Static Timing Analysis Engineer - STA
Competitive salary, plus bonus + benefits

We are looking for a Static Timing Analysis expert to join our client based in Dublin. This is a fantastic opportunity to work on some of the most complex devices ever developed, within a world-class engineering team.

We are looking for an experienced STA Engineer with extensive experience of the latest digital IC design flows to drive full chip Static Timing Analysis and sign-off for a complex, multi-clock, multi-voltage SoC.

This role will suit an engineer with the following:

*Several years' experience working within Digital IC Design, with extensive experience in Synthesis, DFT and floor-planning
*Extensive Static Timing Analysis (STA) and Signal Integrity experience
*Experience with low power design techniques, including low power synthesis and power island implementation
*Experience with Synopsys and/or Cadence EDA tools
*Natural problem solving skills, with a strong attention to detail
*An adaptable / flexible working ethic, and great team work skills

Our client can offer you an exciting, challenging role with plenty of opportunities for long-term career development. A competitive salary and benefits package is on offer, along with visa sponsorship and relocation assistance where needed.

Key skills: Digital ASIC, IC, Design, Physical Design, Backend Design, ASIC, IC, Implementation, chip implementation, RTL, synthesis, STA, static timing analysis, timing closure, VHDL, Verilog, timing constraints, DFT, design for test, DRC, LVS, EDA, Synopsys, ICC, Design Compiler, SoC, system on chip, PrimeTime, IR Drop, analysis, Semiconductor, Dublin, Ireland, Europe.