IC Resources Ltd

ASIC Design Engineer Contract

1 day left

Location
Leuven
Salary
€60 - €70 per hour + initial 3-6 month contract
Posted
03 Apr 2017
Closes
01 May 2017
Ref
J40752
Contact
Paul Wiltshire
Specialist Area
FPGA & ASICS
Contract Type
Contract
Hours
Full Time
ASIC Design Engineer
Leuven Belgium
initial 3-6 month contract
€60-70 per hour

IC Resources are currently working with a client based in Belgium who are looking for experienced IC Design Engineers for an initial 3-6 month contract starting Mid-April.

My client is looking for candidates with experience of working on RTL designs using VHDL or Verilog as they have projects in both. Our client are looking for versatile engineers who have experience with not only the front end RTL design but also have experience of carrying out integration of 3rd party IP, Verification, Synthesis, running the debug loop and having some STA or DFT experience would also be beneficial.

Key Points
- Experience in VHDL/Verilog for RTL design
- Experience in Verification
- Understanding of Synthesis flow
- On-site work in the Belgium
- 3-6 month contract

You must be eligible to work in Belgium for this role, if you would like more information or to apply for this role please contact Paul Wiltshire at IC Resources.

***Please note that if you are interested in the following: RTL design, Digital Verification, Synopsys, Verilog, VHDL, Semiconductors, 3 Months Contract and you could commit to on-site work in Belgium then this could be a good opportunity for you.***

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