Staff Implementation and DFT engineer
Create something that the world is waiting to see!
ARM's Sophia Antipolis design centre is located in one of the most beautiful parts of France, at the heart of Europe's largest and most dynamic technology park. Surrounded by mountains and the Mediterranean Sea, this exceptional design centre has delivered leading products from ARM's Cortex (TM) processor family. These CPUs power some of the world's bestselling smartphones, tablets and gaming systems, using technology that has taken user experience and performance to another level.
Now working on the next generation of processors that will appear in the most desirable products over the next 3 years, the Sophia Antipolis design team is a good combination of very experienced engineers and some of the most talented graduates, coming from the very best engineering schools. Collectively, the team is highly innovative, collaborative, delivery orientated and committed.
Test structure insertion is an essential part of current CPU development. Being able to ensure a good level of testability without impairing performances of a design is a must have for every modern chip.
You will be integrated in CPU design to work on test solution development, verification and integration.
To ease integration it is also important to keep a relevant level of standardization across ARM IP. Hence, you will take part of ARM DFT consortium.
As a member of the Sophia Antipolis CPU implementation team:
You will primarily to take care of Test aspects across Sophia CPU IP: scan insertion, test compression, memory bist, ATPG.
You will have to document, code RTL and validate it, in order to support in-house MBIST interface.
You will support customer with existing IP Test related questions
You will propose and implement improvement to existing methodology and automation
You will take part of DFT standardization across ARM.
It is also expected that you take part of various implementation task on CPU development such as synthesis, Logical equivalence checking and PPA analysis.
Education & QualificationsExtensive years of similar working experience; preferably graduate from a University or Engineering School, in Electronic Engineering or Computer Science.Minimum 2-4 years of experience in ASIC DFT and related subjects.Essential Skills & Experience* Knowledge of DFT techniques, especially memory BIST and scan chains.* Knowledge of RTL coding* Prior exposure to verification techniques and verification testbench support.* Working knowledge of MBIST insertion (Tessent), scan insertion/compression, ATPG.* Understanding of Power/Performance/Area trade-off and floorplanning challenges in typical CMOS design* Experience in ARM based CPUs and systems, especially ARM generic MBIST interface* Ability to schedule own workload and plan tasks* Good communication skills* Able to work in French and in EnglishDesirable Skills & Experience* Working knowledge of Cadence tool chain: Genus, Innovus, QRC, Tempus, conformal* Working knowledge of Synopsys tool chain: DC, ICC, STARRC, PT*, Formality* Prior exposure to formal verification techniques* Experience of developing scripts (tcl, Python, Perl …) for automation purpose* Prior experience in SOC implementation, Sign-off and test can be an advantage* Knowledge of CPU micro-architecture concepts (cache, MMU, pipeline,…)* Working in UNIX/Linux environment, with bug tracking and source code control systems, especially GIT