IC Resources Ltd

Senior Verification Engineer

Excellent package
04 Mar 2017
01 Apr 2017
Andrew Emberson
Job Function
Design, Test
Specialist Area
Contract Type
Full Time
Design Verification Engineer - Ireland

If you want long term career growth and be paid a high salary then this is the time to join my client who are working with very advanced process technologies and are scheduled to grow from 15 to over 40 people over the coming months.

The role:
Design Verification Engineer to join a growing SOC Verification team within a world leader in the mobile industry.

Prerequisites :
The successful Design Verification Engineers will be with proven experience and exposure in a few of the following areas:

- Experience in design, testing and verification in hardware and software on SoCs and SoC subsystems.
- Methodologies for verifying complex units on SoC using industry standard tools and technologies
- Proficient in developing unit and SoC level test benches using OVM/UVM
- Constrained random functional verification environment in System Verilog
- Experience in Gate Level Simulation (GLS) verification flow for SoC verification.
- Experience of pre and post-silicon verification testflow and automated test benches
- Strong knowledge of test-plan generation, coverage analysis transaction level modelling, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog
- Verilog, C/C++, System C, Java, TCL/Perl/shell-scripting required
- Building and leading verification teams is a plus
- RTL design and front end design flow experience

This team is part of a long term commitment to the site, offering considerable opportunity of career growth and advancement.

Please contact Andrew Emberson for more information at Andrew.emberson@ic-resources.com

Key words: Digital, IC, IP, SOC, Verification, Engineer, functional, formal, OVM, UVM, SystemVerilog, assertions, psl, test, random, wireless, CMOS, Semiconductor, Ireland, Europe.