IC Resources Ltd

Principal Digital ASIC Design Engineer - Synthesis / STA

Competitive £££ + attractive benefits
10 Oct 2016
07 Nov 2016
Caroline Pye
Job Function
Specialist Area
Contract Type
Full Time
Principal Digital ASIC Design Engineer - Synthesis / STA

We are seeking a Principal Digital ASIC Design Engineer with strong experience in the areas of synthesis and STA (Static Timing Analysis) to join our client - a world leader in high-precision ICs for the consumer markets.

This role is based in Edinburgh. It's a unique, highly challenging role, with real scope to make a difference to how chips are developed.
Your role will span the entire design flow from front end, back end, to sign off. As a specialist in Synthesis and STA, you will work closely with the digital frontend and physical design teams, and take ownership for synthesis and timing constraints. You will drive and refine the synthesis flow, constraints definition and timing sign-off across IP and chip level.

The ideal candidate for this role will be skilled in RTL design, have a strong understanding across the complete digital ASIC design flow, with particularly strong expertise in synthesis and constraints.

*University degree in Electrical Engineering or related field
*Strong knowledge of the RTL to GDS2 digital ASIC design flow
*Thorough understanding of static timing analysis (STA) and timing closure
*Strong skills in block level synthesis
*Skills in RTL design (however we are not looking for RTL designer)
*Scripting and flow automation experience

This role will suit a dynamic person, capable of driving some parts of the methodology across the team. It's a very versatile opportunity for someone looking to make this role their own.

A competitive basic salary, together with annual bonus scheme, pension scheme, generous holiday allowance plus many other benefits are on offer.

For the right candidate, relocation assistance and visa sponsorship can be provided where necessary.

For details, please contact Caroline @ IC Resources.

Key skills: Digital, ASIC, design, IC, RTL, Verilog, VHDL, synthesis, timing closure, STA, static timing analysis, GDS, GDSII, GDS2, physical design, backend, back end, front end, EDA, Synopsys, Cadence, constraints, timing constraint, Physical Verification, scripting, tcl, perl, signoff, tape out, Semiconductor, circuit design, Edinburgh, Scotland, UK.

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