IC Resources Ltd

Senior Digital ASIC Design Engineer - Munich

Location
München (81249)
Salary
€75000 - €95000 per annum + Depending on experience + Benefits
Posted
07 Sep 2016
Closes
05 Oct 2016
Ref
J37269
Contact
Caroline Pye
Specialist Area
FPGA & ASICS, Semiconductors, Systems
Contract Type
Permanent
Hours
Full Time
A superb opportunity for a Senior Digital ASIC Design Engineer to join growing IC Design team, based in Munich.

Our client is essentially one of the biggest names on the planet in consumer electronics; renowned for sheer excellence in hardware and software design. They are looking to hire a best in class in engineering talent, across Digital, Analog and Mixed Signal Design. For the Digital hire, they are seeking an experienced Digital ASIC Design expert with strong experience working on mixed signal chip sets. This position offers unparalleled challenge and opportunity; a truly exciting chance to be part of a new ASIC development venture in Munich.

The successful Digital IC Design Engineer will work closely with the systems team to develop detailed design specifications and implement the function in Verilog RTL. This team is scheduled for significant growth over the coming year; hence the Senior Digital IC Design Engineer will play a fundamental role in the digital design effort for mixed-signal circuits for consumer devices, and the subsequent growth of the team.

The successful Digital ASIC Design Engineer will have:
A Master degree (preferred) in Electronic Engineering, or similar
*Established experience in Digital IC / ASIC Design, with expertise in RTL coding (Verilog / VHDL)
*Knowledge of the best practices with respect to implementation of digital logic
*Strong Understanding of digital design flow including
-RTL simulation
-logic synthesis
-timing constraints and timing closure
-static timing analysis (STA)
-gate level simulation and equivalence checking

Excellent communication skills in English are required with knowledge of the German language an asset.

Please contact Caroline at IC Resources to apply.

Applicants with experience in the following; Semiconductor, Digital, IC, ASIC, SoC, RTL, Verilog, VHDL, synthesis, STA, timing analysis, timing closure, mixed-signal can be considered for this position. Location: Munich, Germany.

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