Junior / Mid Level ASIC CPU Verification Engineer - France
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Junior / Mid Level ASIC CPU Verification Engineer - Sofia Antipolis - France
My client is looking for a proactive Junior / Mid Level ASIC CPU Verification Engineer (systemVerilog, OVM, VMM, Verilog) to join their highly specialised team, working on innovative and efficient ASIC verification techniques for their high performance, low consumption RISC processors. Their technology lies at the heart of most advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. This exciting multinational company designs the world's most advanced IP, and is looking for a talented ASIC verification expert to pioneer new technologies at their site in Sofia Antipolis.
The ideal candidate will have 2-5 years' experience in a relevant position, strong French and English language skills and:
* A thorough understanding of the current verification strategies required for complex IP development, including constrained random, coverage driven, formal and assertion-based techniques, as well as an understanding of CPU architecture
* Experience of architecting and implementing verification solutions for complex RTL designs.
* Experience of testbench development in high level verification languages such as SystemVerilog, Specman, Vera and SystemC using OVM or UVM techniques.
* Experience in VHDL, Verilog, Perl, Python, TCL, assembly languages and programming experience in C/C++, Unix and Shell
This is an extremely exciting opportunity with scope for career progression and skill acquisition. Effective problem solving and communication skills are essential, as well as a 1st or 2:1 in a relevant degree.
You will need to have the enthusiasm, drive and initiative to be at the forefront of advanced IP, with the initiative to work at an architectural level, and the attention to detail required at the implementation level.
If you are interested in applying for this position please contact me for further details.
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