Graduate Digital Verification Engineer - Austria
This job has now expired
An exciting opportunity has become available in Austria for an ambitious Graduate Digital Verification Engineer.
Based on a strong foundation of providing innovative solutions for over 20 years, my client offers a broad portfolio of highly integrated, end-to-end solutions targeting Next Generation Networks and the Digital Home. These advanced SoC (system-on-chip) solutions address a wide variety of technologies, including VDSL, ADSL2+, SHDSL and VoIP, and have allowed my client to become the number one supplier of Access Network Integrated Circuits.
In this position you will reinforce the digital engineering team implementing & verifying integrated circuits for my clients' mixed-signal telecommunication IC.
The ideal candidate will have a PhD or MSc in a relevant subject and project experience of;
*Verilog / VHDL / Hardware Verification (systemVerilog, UVM)
*Perl, Tcl/Tk, Shell, C++
*Static Timing Analysis (STA) and Synthesis
This is a unique opportunity to join a rapidly expanding company offering fantastic career and skills development opportunities, as well as an exceptional salary and company benefits package.
In this role you will enjoy a small team environment, with the flexibility and innovation that comes from working within a world-leading company. You will need to be self-motivated and able to make a contribution in a variety of different areas.
If this sounds like your next career move then please contact firstname.lastname@example.org to apply or for further details.
Keywords: Digital, ASIC, SoC, Hardware, Software, Mixed Signal, Mixed-Signal, Verification, Research, Development, Formal, Jasper, Formality, communications, telecommunications, telecommunication, Networking, Network, IP, STA, static timing analysis, synthesis, micro-architecture, PhD, MSc, Graduate, RISC, Microprocessor, ARM, EDA, UNIX, LINUX, Tcl, Perl, C, C++, IC Design, cadence, mentor graphics, top level, block level, EDA, RTL Design, RTL Coding, power analysis flows, implementation, logical synthesis, makefile, low power, CPU, GPU, DRC, Synopsys, Xilinx, Altera, Microsemi, Lattice, FPGA, RTL, Design, OVM, VMM, UVM, systemVerilog, VHDL, Verilog, testbench, Semiconductor, Villach, Austria, Europe, Job
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