Senior Digital ASIC Design Engineer - Cambridge
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In this small but dynamic team of digital and analog engineers the Senior Digital ASIC Design Engineer will be responsible for the full front-to-back end design flow process of digital control circuits (up to ten thousand logic gate equivalents) using Verilog, and subsequently implementing circuits on FPGA-based emulator platforms.
*A good degree in Electronic Engineering or similar (BSc/MSc/PhD)
*Extensive experience of digital ASIC design, with thorough RTL expertise in Verilog
*Good knowledge of the backend design flow, with experience with place-route tool flows
*Experience of designing digital blocks for small ICs addressing high volume consumer applications would be very fitting for this role
*Familiarity with FPGA design and prior experience using such instruments as oscilloscopes and logic analysers for debugging designs would be ideal
Contact Caroline Pye, ASIC Recruitment Specialist for more information.
Key words: Fabless semiconductor startup seeks a Senior Digital ASIC Design Engineer with skills in: digital, IC, ASIC, FPGA, design, RTL, VHDL, Verilog, front end, RTL, analog, mixed signal, CMOS, verification, back-end, synthesis, STA, static timing analysis, EDA, place and route, PNR, P&R.
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