Junior Design Methodology Engineer - Chip - Package - Austria
This job has now expired
In this role you will be responsible for the flow and methodology development for both IC Designers and Package Designers.
*Evaluation of EDA tools
*Analysis and methodology definition for chip and package designers
*Specification and implementation of scripts inside the EDA tools or within a Linux and Windows environment
*Coordination of feature/software development activities at EDA vendors
*Overall flow and methodology test and QA
*Tool, component, flow and regressions test
Responsibilities includes the development of design flows for leadframe packages, which bridges the gap between mechanical CAD (package design environment in AutoCAD) and electrical CAD (chip design environment in Cadence Virtuoso or Cadence Encounter), including connectivity entry, physical layout design of the leadframe and the bonding diagram, DRC, LVS, and the link to electrical and thermal simulation of the complete system of chip and package.
Strong communication skills in English is required with German, a strong asset. The ability to work well within a diverse and international team is essential.
If your looking for an opportunity to learn and expand your experience then this could be the job for you.
Contact Leon at IC Resources today to apply. firstname.lastname@example.org
Key words: Methodology, CAD/EDA Support, IC Designers and Package Designers, mechanical and electrical CAD, Cadence Virtuoso, Cadence Encounter, DRC, LVS, Java, Perl, Tcl. Location: Europe, Austria.
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