Physical Design Engineer - Cambridge, UK
This job has now expired
You will work as part of a specialised team to analyse and optimise cutting edge GPU designs, and will implement and verify ASIC designs of varying size and complexity, and develop new methodologies to improve the efficiency and quality of my client's GPU implementations.
This exciting multinational company designs the world's most advanced IP, and due to ever increasing demand for their high performance, low consumption 3D graphics processors are expanding their GPU teams across the globe.
The ideal candidate will have;
* Experience of ASIC implementation challenges on cutting edge process nodes.
* Experience with running Logical Synthesis and STA, as well as top and/or block level floor planning, Place and Route, CTS, logical and physical optimization, logical equivalence checking, timing closure and power analysis flows.
* Good scripting skills using Tcl, Perl, Makefile and Shell scripts, as well as experience with low power design techniques, Verilog RTL Design, Physical Verification (LVS and DRC), power grid design/analysis and static and dynamic IR-drop analysis.
This role will involve interfacing closely with EDA Vendors and customers, so good communication skills and team working abilities are essential to this role, as well as the ability to learn and promote the use of new techniques and methodologies within projects.
This is a unique opportunity to join a rapidly expanding company offering fantastic career and skills development opportunities, as well as an exceptional salary and company benefits package.
If this sounds like your next career move then please contact email@example.com to apply or for further details.
Keywords: Digital, ASIC, SoC, Hardware, Software, Verification, Physical Design, Back-end, RISC, Microprocessor, ARM, EDA, UNIX, LINUX, Tcl,Perl, C, C++, IC Design, cadence, mentor graphics, top level, block level, floor planning, Place and Route, CTS, logical optimization, physical optimization, logical equivalence checking, timing closure, STA, EDA, RTL Design, RTL Coding, power analysis flows, implementation, logical synthesis, makefile, low power, CPU, GPU, DRC, Physical Verification, power grid design, power grid analysis, static, dynamic IR-drop analysis, Synopsys, Xilinx, Altera, Microsemi, Lattice, FPGA, RTL, Design, OVM, VMM, UVM, SystemVerilog, VHDL, Verilog, testbench, Semiconductor, Cambridge, UK, Europe
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