Graduate /Junior Verification Engineer - Cambridge, UK
This job has now expired
A bright Junior Verification Engineer with excellent RTL design and complex verification skills (Verilog, systemVerilog) is sought for a challenging and varied role involving the design, implementation and verification of digital modules for my clients' range of wireless chips, to provide new features and enhancements to their existing chips.
This is a unique role with a particular emphasis on a variety of verification tasks, from working on smaller blocks all the way up to large IP verification, and also involves coding in RTL.
Multi-skilled individuals are highly valued within the team, but there are also opportunities for specialization in many areas, as well as the opportunity to move into a more design focussed role in the future.
The ideal candidate will be degree qualified and have experience of;
*Complex digital verification and design techniques and languages, including RTL coding, Verilog, systemVerilog or VHDL
*Scripting in TCL, Perl or Python
*Writing testbenches and OOP techniques
Bright engineers with the ability to gain an understanding of existing complex designs and to assist in their verification are sought for this role, enthusiasm and determination are as important as technical ability, and training on Verilog and systemVerilog can be provided by senior members of the team.
Good communication skills and team working abilities are essential attributes , as you will be working within a small team offering a close knit working unit, but also the financial backing of a large international company, which will allow a promising engineer to quickly gain new technical skills and a flourishing career.
Candidates must be eligible to work in the UK.
If this sounds like your next career move then please contact firstname.lastname@example.org to apply or for further details.
Keywords: Digital, ASIC, SoC, Hardware, Software, Verification, RISC, Specman e, Microprocessor, ARM, EDA, UNIX, LINUX, Tcl,Perl, systemC, Vera, Specman e, E Language, C, C++, IC Design, testbench, testplan, object oriented, constrained random, ABV, scoreboard, RTL simulation, travel, cadence, mentor graphics, Synopsys, Xilinix, Altera, Microsemi, Lattice, FPGA, RTL, Design, OVM, VMM, UVM, SystemVerilog, VHDL, Verilog, testbench, Semiconductor, Cambridge, UK, Europe
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