ASIC Verification Engineer - Spain
This job has now expired
As part of their rapid expansion, with a view to launching the first of their highly desirable products at the end of the year, this innovative company is looking for an ASIC Design Engineer to join their experienced IC Design Team. The successful candidate will be responsible for the design of test-benches for verification of complete ASICs, starting at the block-level and ending with chip-level test-bench definition, implementation and debug. This work will also be completed with RTL design of some blocks and FPGA debugging.
1.Strong background on digital ASIC verification: test-case generation, random and directed stimuli generation, regression management.
2.Knowledge of Verilog HDL is a must and knowledge of SystemVerilog and SystemC is also desired.
3.ASIC/SOC design flow, DFT.
4.FPGA debugging experience.
5.Knowledge of Matlab, and previous experience in microelectronics are desirable.
This is set to be one of the hottest places in the global electronics industry for engineers to explore their full potential and really make their mark.
Effective problem solving, communication and team working skills are essential, as well as a 1st or 2:1 in a relevant degree. You will also have exceptional English (written and spoken) and the drive to push the boundaries of ASIC Verification.
If this sounds like you please contact Clare for further details.
Key words: Digital, ASIC, SoC, Hardware, Software, Verification, RISC, Specman e, Microelectronics, testcase, FPGA, Matlab, DFT, Verilog HDL, System C, Block Level, Chip Level, Fabless, Digital Communications, Microprocessor, FPGA, RTL, Design, OVM, VMM, UVM, SystemVerilog, VHDL, Verilog, testbench, Semiconductor, Madrid, Spain, Europe
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