I am recruiting for a Senior Digital Physical Design Engineer to join my client's new design branch in Cambridge.
The successful Physical Design Engineer will play a key role in the whole physical implementation task of wireless ICs and SoCs from RTL to GDSII. This will involve close work with digital, analogue and package design teams, as well as providing peer reviews and interfacing with EDA tool vendors to ensure smooth running of the digital implementation process. The group is scheduled to grow extensively over coming years hence there's excellent scope to climb the career ladder within this organisation.
Requirements:
*A number of years' experience in physical implementation, with a proven track record of technical success
*A detailed understanding of the RTL-GDSI flow, with hands-on experience in STAM floorplanning, Place & Route (P&R), timing closure
*Experience with low power design techniques
*Synopsys tool experience is highly desirable
Contact IC Resources today.
Key words: Digital, Physical, Backend, Design, Implementation, RTL, GDSII, GDS2, layout, floorplanning, Place & Route, P&R, PnR, timing analysis, STA, timing closure, CTS, clock tree synthesis, EDA, Synopsys, signal integrity, physical verification, Verilog, scripting, perl, python, TCL, Semiconductor, South East, East Anglia, Cambridge, UK.
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