Design Verification Consultant, San Jose, CA.
This job has now expired
This is no ordinary engineering role, you will join a fast-paced, team-oriented environment, developing and delivering training material covering complex topics such as Verilog, SystemVerilog, UVM, SystemC and TLM.
Working with many different semiconductor companies you will provide customized training and leading edge consultancy in ASIC/SoC design and verification.
To be successful in this role you will need to be an experienced VLSI engineer with excellent communication skills, and a passion for imparting knowledge to others.
Advanced knowledge is required in one or more of the following hardware description languages: VHDL, Verilog, SystemVerilog, 'e', OpenVera and/or SystemC.
A willingness to travel is necessary since approximately one third of your time will be spent away from home at client sites.
Keywords: VLSI, Verilog, SystemVerilog, training, UVM, methodology, San Jose, USA
IC Resources - your first contact for ASIC / SoC / Analog / RF IC jobs in USA.