Superb new DFT opportunity with established Semiconductor client in Cambridge.
My client has an immediate vacancy for a DFT (Design for Test) Engineer to join its leading wireless ASIC team based in Cambridge.
Requirements must include:
*A good degree (BSc/MSc/PhD) in Computer Science, Electronic Engineering or relocated field
*Strong experience in DFT for digital ASIC designs
*Skills in scan and DFT insertion, ATPG pattern generation, memory BIST and JTAG
*Experience using Mentor or Synopsys DFT tools
*A good all-round knowledge of digital ASIC design, with experience using Verilog language
Exceptional career prospects await with this company. If you are a high calibre engineer with strong academics and relevant DFT expertise, please email your CV to Caroline at IC Resources.
Key words: DFT, Digital, SoC, ASIC, RTL, Boundary, scan, insertion, ATPG, BIST, JTAG, test, ATE, EDA, Synopsys, Mentor, debug, yield, test pattern generation, Semiconductor, Cambridge, East Anglia, UK.
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