A unique opportunity has arisen for an experienced Digital Physical Design Engineer to join our IC design client based in exotic Malaysia.
With an enviable customer portfolio, our client is rapidly expanding and seeks an experienced Physical Designer to join them working on complex ICs in state-of-the-art CMOS process technologies. You will be responsible for design floor planning, Place and Route (P&R), timing closure, parasitic extraction, static timing analysis (STA) and Physical verification (DRC, ERC, LVS), and cover multiple tapeouts, whilst leading / mentoring more junior engineers in the group.
Industry degree qualified (or equivalent) the successful applicant will have established experience in Digital Physical Design/Implementation, with experience using Cadence tools (ideally RTL Compiler or SoC-Encounter), with experience in low power design techniques. The role offers the opportunity to gain experience working on really cutting-edge designs, within a great location!
Contact IC Resources for further details.
Key words: Digital, Physical, Design, Backend, ASIC, Floorplanning, Place & Route, P&R, STA, static timing analysis, parasitic extraction, low power, Cadence, EDA, RTL Compiler, SoC Encounter, analog, Semiconductor, Far East, Malaysia, Asia
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