Senior Verification Engineer - Sheffield - SystemVerilog/UVM
This job has now expired
The ideal candidate will have;
*A high level of competence in Perl or other scripting languages, C/C++, and a verification methodology such as UVM.
*A good understanding of verification planning and metrics, and a high level of pro-activity, initiative and problem solving
*Experience of Verilog or VHDL hardware design, and/or AMBA (AHB/AXI/ACE) based SoC architectures
*Experience Power Aware verification with UPF, and/or experience of software based hardware verification using accelerated platforms such as emulators or FPGAs.
Energy and organisational skills are highly important attributes, as well as the desire to continually advance verification capabilities. This person will have great communication and interpersonal skills, and be able to engage actively with the team and across all business groups. Due to an increasingly high demand for their market-leading products, my client has rapid growth planned for 2012, making this an exciting time to join and grow within this world-leading company.
A competitive salary (based upon experience) is on offer, along with benefits including Holiday, Pension, Private Health Care, RSUs, Visa Sponsorship, Relocation Allowance, Subsidised Gym Membership and more.
If this sounds like your next position please contact firstname.lastname@example.org for further details.
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Key words: Digital, ASIC, SoC, Hardware, Software, Verification, RISC, Specman e, System C, E- Code, Microprocessor, FPGA, RTL, Design, Perl, TCL, OVM, VMM, UVM,C, C++, Vera, SystemVerilog, VHDL, Emulation, Structured Programming Techniques (OOD), RTL Verification, Network-on-Chip, Software Development, 2D, 3D, Graphics, Architecture, Specman, Verilog, testbench, Semiconductor, Sheffield, UK