Key words: DFT, Design for Test, Synthesis, Equivalence, check, ASIC, IC, Design, backend, place & route, P&R, STA, floorplanning, DRC, LVS, IR, wireless, 3G, 4G, WiMAX, PHY, LTE, Paris, France.
This is an excellent opportunity for a Senior Design-for-Test (DFT) Engineer to join a prominent Semiconductor company working on the latest 4G wireless technology.
Working with the ASIC team, you will make a significant contribution to the development of next generation WiMAX and LTE SoC in deep submicron technology. In this role you will drive synthesis, DFT, and equivalence checking activities, and be a key interface between the frontend ASIC team based in Paris and the backend team based in Singapore.
The successful candidate will have a very established background in digital IC design, with particular emphasis on synthesis, DFT, and equivalence checking. A thorough knowledge of the backend design flow is required, together with of course excellent communication skills for liaising with international teams.
Experience in any of the following would be a bonus:
*Experience using Cadence tools
*DRC, LVS, and IR drop analysis
*Power gating
Contact IC Resources today for further details.
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