Our key Image Processing client is searching for a DFT (Design for Test) Engineer to join their design centre located in the Thames Valley.
This is a dual role which will essentially have two main functions:
*Defining the DFT elements for all SoC Designs, as well as taking part in functional design work when required
*Supporting the Product Engineering and Quality Assurance teams with any issues that arise with products from the SoC Design team; this involves representing the team at regular review meetings, identifying areas for further analysis and working with the relevant departments to deduce cause and solution, hence some international travel to the US will be required.
Requirements:
*Several years experience in DFT, including scan insertion, ATPG generation, boundary scan
*Experience of Synopsys Design Compiler / TetraMAX
*Experience using Verilog /System Verilog
*Scripting experience with Perl, tcl
*Ability to debug test structures and support Product Engineering in root cause analysis
*Excellent communication and interpersonal skills
*Willingness and ability to travel overseas from time to time.
Key words: DFT, Design for Test, SoC, Design, Verilog, ATPG, boundary, scan, JTAG, memory, BIST, Synopsys, DC, Design Compiler, Tetramax, test, debug, Semiconductor, UK, South East, Thames Valley
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