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Senior Digital IC Layout Engineer - SoC, CPF - Italy - Contract
My client a global semiconductor company is currently recruiting for an experienced Digital Physical Design engineer with strong knowledge of Cadence encounter CPF flow for an initial 6 month contract in northern Italy.
You will have an extensive background and knowledge of the digital ASIC back end design flow and be able to lend your expertise to make an immediate impact on the company's SoC designs.
Ideal candidates will have expertise in the following areas:
- Timing closure on complex SoC designs
- IR drop analysis
- Cadence Encounter CPF flow
- Conformal LP
- Mentor Calibe for Physical verification
This is a very urgent requirement, immediate start dates apply today with an updated CV to be considered