Principal ASIC Design Engineer - Verilog - Permanent - Northamptonshire
An exciting digital development opportunity is currently available with a rapidly expanding semiconductor company based in Northamptonshire.
You will take the overall responsibility for developing high speed ASIC technology as well as taking the overall lead for a small team of talented design and verification engineers.
Responsibilities
- Technical leadership, digital block level design management and people management
- Definition of chip level architecture specifications and lead the implementation for next generation Mixed-Signal, High speed products
- RTL code implementation using Verilog/System Verilog
- Own pre-layout synthesis and timing closure using Cadence tools
- Work with back-end engineers on post-layout timing closure
- Work with verification engineers to debug test cases in RTL and Gate level simulation environment, define and generate assertion
Essential Experience
- Minimum 10 years experience in multi-million gates digital/mixed signal IC design at 65, 40nm or smaller technology
- Experience of entire design cycle from micro-architecture specification, definition, verilog coding, synthesis and timing closure to post-silicon debug and support in lab environment
- Technical lead experience for a group of 3-5 engineers from micro-architecture specification to silicon
- Experience with both RTL and Gate Level verification and debug
- Experience in coverage based/ random test environment and assertion generation
- High speed serial link (PCI-E, SATA, 10G Ethernet, HDMI/Display Port etc) or DDR2/DDR3 memory controllers would be beneficial
This is a fantastic opportunity to earn a senior role working at the forefront of the development of communications technology. Above market salaries are available for exceptional candidates. Apply today with an updated CV for more information and to be considered