Digital SoC Design Engineer (DFT)
This job has now expired
The successful candidate will join an expert silicon team working on leading edge CMOS designs.
You will be degree qualified in Electronic Engineering or similar, having spent a successful few years as a Digital IC Designer. Specifically, your specialist skills will include RTL Design and functional verification using Verilog and / or System Verilog, as well as Design for Test (DFT and design for debug (DFD).
On the DFT side, your skills will include:
- Scan insertion using Synopsys DC/Cadence RC or similar.
- ATPG generation using Mentor FastScan or Synopsys Tetramax.
- Knowledge of scan structures such as compression logic, on-chip clocking modules.
- JTAG controllers, memory BIST, boundary scan, analog test control.
Contact IC Resources today for further details.
key words: Digital SoC Design Engineer required with strong skills in the following: Digital SoC, IC, ASIC, design, RTL, Verilog, SystemVerilog, debug, test, Design for test, DFT, scan, memory BIST, boundary scan, Mentor TestKompress, Synopsys DFTMax, LBIST architecture, microarchitecture.
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