Principal Verification Engineer

Principal Verification Engineer

A unique opportunity for a Principal ASIC Verification Engineer to join a global firm working in the semiconductor sector has arisen Cambridge.

Working as a Principal Engineer, you will lead the definition, reviewing and implementation of verification strategies, technically support junior engineers, create and review testplans, and technically own verification challenges producing high quality solutions. You will make a significant contribution to the definition and execution of the ASIC verification strategy and there will be the opportunity to take lead responsibility over small projects.

The successful applicant will be a proven ASIC Verification specialist with significant experience in digital ASIC verification using constrained random techniques. Strong skills in Verilog are essential and candidates must be familiar with many forms of validation such as random, directed random, and formal validation including model checking. It would also be useful to have experience or knowledge in some or all of the following as well:

- Hands on experience with SystemVerilog or Specman language and OVM or VMM
- Experience of defining and driving FPGA and/or emulation based testing flows.
- Experience working in the field of graphics and video
- Formal verification skills

For immediate consideration for this role please email your CV to apply-322611968-4996@at.idibu.com.

Key words: ASIC verification, RTL, Verilog, VHDL, SystemVerilog, Specman, e, Vera, SystemC, constrained random verification, functional verification, unix, linux, Assembler, C, C++, validation, CPU, GPU, graphics, video, HDMI, MPEG, processor, microprocessor, OVM, VMM, testbench, FPGA, emulation, semiconductor