ASIC Design and Verification Contract - Germany
This job has now expired
- RTL in Verilog
- Knowledge in the Front - End Design Flow
- Experience in Verification
An important client of IC Resources is requiring an experience ASIC Design and Verification Engineer who has experience in the complete front-end design flow including verification. Knowledge in SystemVerilog and VMM or alike would be beneficial but are by no means essential. The contract will start at the beginning of May and run for 6 months with a likely possibility of an extension.
If you feel you have the necessary experience and knowledge to fulfil the requirements of this position then please do not hesitate to contact Tom Huggins at IC Resources.
Notes: 6 months, Verilog, VHDL, Design, Verification, RTL, ASIC, VMM, UVM, OVM, Germany
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