Our world-leading Semiconductor client based in Norway is seeking a skilled Digital Physical Design Engineer to join them working on the very latest cutting-edge Graphics Processors.
The successful candidate will join the Chip Implementation team to implement and verify designs of varying complexity using front and/or back-end design flows. The right candidate for this position will be someone with a strong profile background in Digital Physical Design, with strong skills in Logical Synthesis and STA (Static Timing Analysis), floor planning, Place and Route (P&R), timing closure, physical verification (LVS and DRC). Ideally you will also have a good understanding of front-end RTL design (in Verilog) and DFT, however these aren't 100% essential.
Our client offers the chance to work on some of the most advanced processor technology and IP in the world - if this sounds of interest, contact Caroline @ IC Resources for further details.
Work permits and relocation assistance can also be provided.
Key words: ASIC, RTL, GDSII, GDS2, SoC, Physical Design, Backend, synthesis, STA, static timing analysis, floor planning, Place& Route, P&R, PnR, timing closure, tape out, physical verification, RTL, CTS, clock tree synthesis, scripting, perl, tcl, Shell, Semiconductor, Norway, Scandinavia, Europe.
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